Renesas Electronics Corporation, a leading provider of advanced semiconductor solutions, has introduced three new System-on-Chip (SoC) technologies designed for automotive multi-domain electronic control units (ECUs). These solutions integrate advanced AI processing and chiplet capabilities, forming a core platform for next-generation automotive electrical and electronic (E/E) architectures. The company showcased these innovations at the International Solid-State Circuits Conference (ISSCC) 2026, held February 15–19 in San Francisco.
As the industry moves toward software-defined vehicles (SDVs), automotive SoCs must deliver high performance to handle multiple applications simultaneously while offering scalability through chiplet integration. They also need to meet stringent functional safety standards. With central computing SoCs becoming larger and more complex, ensuring automotive-grade reliability is increasingly challenging. At the same time, rising performance levels drive higher power consumption, making energy efficiency and safety critical priorities. Renesas developed these new technologies to address these evolving demands.
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1. Chiplet architecture that supports functional safety
To address the stringent functional safety demands of automotive SoCs, Renesas has introduced a proprietary architecture capable of supporting ASIL D compliance, even within chiplet-based designs. By integrating the standard UCIe die-to-die interface with its own RegionID mechanism, the architecture ensures that hardware resources remain isolated when multiple applications operate concurrently, enabling true Freedom from Interference (FFI).
Traditional UCIe interfaces do not support the transfer of RegionIDs across dies. Renesas resolved this by mapping RegionIDs into the physical address space, encoding them within the UCIe region, and transmitting them accordingly. This approach allows secure access control via the memory management unit (MMU) and real-time cores, ensuring functional safety across chiplets. Testing also confirmed that the UCIe interface sustains processor-to-memory bandwidth at speeds up to 51.2 GB/s, close to the maximum intra-SoC transfer rate, delivering both high scalability and safety for advanced automotive applications.
2. Advanced AI processing capabilities and automotive-grade quality
Automotive-grade reliability remains a critical requirement for software-defined vehicle (SDV) systems. Renesas has developed a 3 nm SoC that enhances neural processing unit (NPU) performance for AI workloads while preserving stringent automotive quality standards. As NPUs have grown approximately 1.5 times larger than previous generations, increased clock latency between shared clock sources and circuit blocks has become a challenge. To overcome this, Renesas reengineered its clock architecture by breaking traditional module-level clock pulse generators (CPGs) into smaller mini-CPGs (mCPGs) at the sub-module level. This approach significantly reduces clock latency and ensures timing accuracy.
Introducing multiple layers of mCPGs, however, adds complexity to test clock synchronization—an essential factor in meeting zero-defect automotive targets. Renesas addressed this by embedding dedicated test circuits within the hierarchical CPG structure and unifying the signal path for both operational and test clocks. During test mode, upper- and lower-level mCPGs are synchronized under a single clock source, enabling precise phase alignment. This design achieves zero-defect quality standards even in large-scale SoCs, delivering the reliability required for next-generation SDVs.
3. Advanced power control and monitoring for improved power efficiency and safety
To deliver the performance levels demanded by automotive SoCs while improving power efficiency and safety, Renesas introduced an advanced power gating architecture featuring more than 90 distinct power domains. This allows highly granular power control, ranging from a few milliwatts to several tens of watts depending on system requirements. To address IR drops caused by higher current densities in advanced process nodes, Renesas divided power switches (PSWs) into ring and row configurations. The ring PSW limits inrush current during power-up, while the row PSW balances impedance across the domain. Together, these measures reduce IR drops by approximately 13% compared to conventional designs.
To comply with ASIL D safety standards, Renesas implemented a dual core lock step (DCLS) architecture in which master and checker cores operate with independent power switches and controllers. This ensures that faults in one core can be identified through lockstep comparison. Each PSW gate signal is also monitored through loopback mechanisms to detect failures, particularly in OFF states. Additionally, a temperature-resilient digital voltage monitor (DVMON) enhances voltage supervision and improves aging tolerance by 1.4 mV. These combined innovations enable high-performance automotive SoCs with optimized efficiency and robust functional safety.
These new technologies are being used in Renesas’ R-Car X5H SoC for automotive multi-domain ECUs. With R-Car X5H, users can accelerate the evolution of SDVs while ensuring safety and enabling autonomous driving, digital cockpit and more.
